4.79b04
~~~~~~~~~~~~~
???

4.79bFIXED
~~~~~~~~~~~~~
Rus

᫨  ন SSE4.2 (2008+ . 㤥   ⭮⥫쭮 ᮢ६묨),   믮  ꥬ 16  (  8 ),  ᯥ稢   १ (   楫  L3,   㠫 楢). 
//  32 : MemSizePriznak = 3; ResultsNew DB 13 DUP(0) -> 14. 㤥 뢠  32   32 .

஬ ⮣,   ࠭ ⥯ ⮡ࠦ ᨬ쭠  SSE, ন ஬ (ࠧ    ।).

ࠢ ९  㬭,  ᪮  > 40/.   । .

ࠢ 뫥  vmware (  Bochs/Qemu,  ⠬  㦥 業 ). 뫠 ୮ ⠭  権 (tnx Claude).   ⠥ .

襭 ⠭    ࠧ  'Average/Max seek time'   HDD.   ଠ쭮 ⮡ࠦ  SSD.

ࠢ ⮡ࠦ   ஢ Core2 (  cpuid ᥪ  PIII).

襭  Memory Bandwidth  Core2+, 㢥祭 ࠧ 㥬   8-16 (  室  ).  ⪫祭 GetMemPeakBandwidth128,  ⠬  襭 १.

ࠢ । Cyrix MII / Cyrix 6x86MX, ᫮  4.73 (?)

* *. 뢠  (Speed via TSC) ᮮ⢥     ࡮-⮬,   䠪᪮.   (Intel । 뢠 १ APERF / MPERF)


Eng

- The cache test now uses a 16 MB test size (instead of 8 MB) on CPUs supporting SSE4.2 (2008 and later, considered relatively modern). This provides more realistic results by preventing the test from fitting entirely in the L3 cache on modern CPUs.
  // For 32 MB: MemSizePriznak = 3; ResultsNew DB 13 DUP(0) -> 14. The displayed range will be from 32 KB to 32 MB.

- The main screen now displays the highest SSE version supported by the CPU, since this information is already detected.

- Fixed an integer overflow during multiplication at cache speeds above 40 GB/s, which could break cache detection logic.

- Fixed crashes in VMware (also in Bochs/QEMU, although a full BIOS implementation is still needed there). Instruction lengths were being calculated incorrectly (tnx Claude). The assembler now handles instruction length calculation automatically.

- Reduced the constant affecting the display of the *Average/Max Seek Time* section in the HDD test, allowing it to display correctly on SSDs.

- Fixed incorrect display of certain Core 2 CPU information due to CPUID values overlapping with those of the Pentium III.

- Improved the Memory Bandwidth test on Core 2 and newer CPUs by increasing the test memory size to 8-16 MB (to prevent the test from running entirely out of cache) and disabling `GetMemPeakBandwidth128`, which produces inflated results on these CPUs.

- Fixed the detection of Cyrix MII / Cyrix 6x86MX, which was broken in 4.73 (?)

- *Not a bug:* The displayed (Speed via TSC) reflects the CPU's base frequency with Turbo Boost factored in, rather than its instantaneous operating frequency. This is by design. Intel recommends calculating the actual frequency using APERF/MPERF.
