 lib environment
 lib dtab
 lib sptab
 lib pprtab
 lib inttab
 lib bfhdr
 lib blktab
 lib chrtab
 data
 sttl Device Driver Tables
 pag
 name devtab
 define

*
* System Parameters - adjust accordingly
*

SSIZE equ 1 initial stack size (*PAGSIZ)
MAXJOB equ 20 maximum simult user tasks
NBLKS equ 16 Accessable pages in address space
USRHIP equ NBLKS-1 User's highest addressable page
USRHIP_4 equ USRHIP<<4

* terminal i/o constants

OQHI equ 119 outq upper limit
OQLO equ 15 outq lower limit
CHRLIM equ 255 max characters on q

*
LIGHTS fcb 0

*
* Machine constants
*

DATBOX equ $FFF0 memory mapper regs
BLKHOL equ $F3 black hole memory cell
DSKTRM equ BLKHOL swap map terminator
WHTHOL equ $F4 white hole memory cell
CLOCK equ $E210 gimix clock base
HZTIM equ 12500+1 gimix clock rate
CLKSEL equ CLOCK+1 clock select and status register
CLKLAT equ CLOCK+6 clock timer latch
CLKCON equ %01000001 clock control (gimix)
CLKMSK equ %10000000 clock interrupt mask
*
* Device Register Definitions
*
*  DMAF2
*
DMFINT equ $F000 dma interrupt register
DMFADR equ DMFINT+2 dma address register
DMFCCR equ DMFINT+1 dma control register
DMFCOM equ DMFINT+4 wd command register
DMFTRK equ DMFINT+5 wd track register
DMFSEC equ DMFINT+6 wd sector register
DMFDAT equ DMFINT+7 wd data register
DMFDRV equ DMFINT drive select register

*
* CMI 5" Winchester
*
CMICMD equ $F100 disk command register
CMIADR equ CMICMD+1 DMA address registers
XBCCOM equ CMICMD+4 Xebec Command Register

*
* DMF3 (Floppy)
*
DMF3ADR equ $F300 dma address register
DMF3CNT equ DMF3ADR+2 dma count register
DMF3CCR equ DMF3ADR+$10 dma control register
DMF3PRI equ DMF3ADR+$14 dma priority register
DMF3INT equ DMF3ADR+$15 dma interrupt register
DMF3COM equ DMF3ADR+$20 wd command register
DMF3TRK equ DMF3ADR+$21 wd track register
DMF3SEC equ DMF3ADR+$22 wd sector register
DMF3DAT equ DMF3ADR+$23 wd data register
DMF3DRV equ DMF3ADR+$24 drive select register
DMF3LAT equ DMF3ADR+$25 controller addr latch
VIA    equ DMF3ADR+$40 via thing

*
* Archive Tape (DMF3)
*

DMA equ DMF3ADR address of tape controller DMA

AT_C2A equ DMA+08 channel 2 address register
AT_C2C equ DMA+10 channel 2 count register
AT_C3A equ DMA+12 channel 3 address register
AT_C3C equ DMA+14 channel 3 count register
CAT_C2 equ DMA+18 channel 2 control register
CAT_C3 equ DMA+19 channel 3 control register
AT_PTY equ DMA+20 priority control register
AT_ICR equ DMA+21 interrupt control register
AT_DCR equ DMA+22 dma data chain register

TAPE equ DMF3ADR+$40  address of tape controller VIA

AT_DTB equ TAPE+00 B-Side Data Register
AT_DTA equ TAPE+01 A-Side Data Register
AT_DRB equ TAPE+02 B-Side Direction Register
AT_DRA equ TAPE+03 A-Side Direction Register
AT_T1C equ TAPE+04 Timer 1 Counter Register
AT_T1L equ TAPE+06 Timer 1 Latches
AT_T2C equ TAPE+08 Timer 2 Counter Register
AT_VSR equ TAPE+10 Shift Register
AT_ACR equ TAPE+11 Auxillary Control Register
AT_PCR equ TAPE+12 Peripheral Control Register
AT_IFR equ TAPE+13 Interrupt Flag Register
AT_IER equ TAPE+14 Interrupt Enable Register
AT_DXA equ TAPE+15 A-Side Data Register

AT_XAL equ DMF3ADR+$25 extended address latch

AT_ATR equ DMF3ADR+$52 archive RESET
*...... THE ABOVE RESET TOGGLE DOESN'T WORK BECAUSE OF TIMING CONSTRAINTS
AT_DMC equ DMF3ADR+$53 archive DMA clear
AT_DMP equ DMF3ADR+$60 archive DMA preset

*
* DMF3 Winchester Equates
*
board      equ     DMF3ADR             DMF3 base address

extaddr    equ     board+$25           74LS374 latch for 4 extended address
*                                      lines (bits 0-3),
chan0      equ     %00000000           dma channnel select
chan1      equ     %00010000           (bits 4-5),
chan2      equ     %00100000
chan3      equ     %00110000
dmahalt    equ     %10000000           dma halt mode
dmabusreq  equ     %00000000           dma bus req (low)
archread   equ     %01000000           archive edge select high (READ)
archwrite  equ     %00000000           archive edge select low (WRITE)


auxdecode  equ     board+$50           74LS139 for misc. decodes
*                                      (all four lines strobed with lda label)
hld_toggle equ     auxdecode+0         head load toggle
wd1000_res equ     auxdecode+1         winchester software reset
arch_res   equ     auxdecode+2         archive reset
arch_clr   equ     auxdecode+3         archive clear

dma_preset equ board+$60

dma        equ     board+$00           68B44 dma controller

*   memory register definitions:
dmac0a     equ     dma+$00                 channel 0 address register
dmac0c     equ     dma+$02                 channel 0 byte count register
dmac1a     equ     dma+$04                 channel 1 address register
dmac1c     equ     dma+$06                 channel 1 byte count register
dmac2a     equ     dma+$08                 channel 2 address register
dmac2c     equ     dma+$0a                 channel 2 byte count register
dmac3a     equ     dma+$0c                 channel 3 address register
dmac3c     equ     dma+$0e                 channel 3 byte count register
*
*   channel control register definitions:
*
dmacc0     equ     dma+$10                 channel 0 control register
dmacc1     equ     dma+$11                 channel 1 control register
dmacc2     equ     dma+$12                 channel 2 control register
dmacc3     equ     dma+$13                 channel 3 control register

dmadend    equ     %10000000           1 => dma transfer complete
dmabusy    equ     %01000000           1 => transfer in progress
dmacntd    equ     %00001000           1 => address down count
dmadmar    equ     %00000001           1 => dma memory read
dmasteal   equ     %00000100           cycle steal dma mode
dmaburst   equ     %00000010           halt burst mode
dmahbyte   equ     %00000000           halt byte mode
*
*   priority control register definition:
*
dmaprc     equ     dma+$14                 priority control register

dmare0     equ     %00000001           1 => channel 0 request enabled
dmare1     equ     %00000010           1 => channel 1 request enabled
dmare2     equ     %00000100           1 => channel 2 request enabled
dmare3     equ     %00001000           1 => channel 3 request enabled
dmarotat   equ     %10000000           1 => rotate dma channel requests
*
*   interrupt control register definition:
*
dmaicr     equ     dma+$15                 interrupt control register

dmadie0    equ     %00000001           1 => enable irq on channel 0 dend
dmadie1    equ     %00000010           1 => enable irq on channel 1 dend
dmadie2    equ     %00000100           1 => enable irq on channel 2 dend
dmadie3    equ     %00001000           1 => enable irq on channel 3 dend
dmadirq    equ     %10000000           1 => dma irq is set
*
*   data chain register definition:
*
dmadcr     equ     dma+$16                 data chain control register

dmacsel    equ     %00001000           1 => four channel select
dmadce     equ     %00000001           1 => data chain enable
dmadcc     equ     %00000110           data chain channel select


wd1000     equ     board+$30           WD1000 5-1/4 winchester controller

wd_data    equ     wd1000+0            data register

wd_error   equ     wd1000+1            error register (read only)
*                                      bit 7 bad block detect
*                                      bit 6 CRC error, data field
*                                      bit 5 CRC error, ID field
*                                      bit 4 ID not found
*                                      bit 3 unused
*                                      bit 2 Aborted Command
*                                      bit 1 TR000 (track zero) error
*                                      bit 0 DAM not found
wd_wr_pre  equ     wd1000+1            write precomp (write only)

wd_sec_cnt equ     wd1000+2            sector count (during format)

wd_sec_num equ     wd1000+3            sector number

wd_cyl_low equ     wd1000+4            cylinder (low byte)
*                                      C0-C7
wd_cyl_hi  equ     wd1000+5            cylinder (high byte)
*                                      C8-C9

wd_sdh     equ     wd1000+6            size/drive/head
*                                      bit 7 XX,
*                                      bit 6,5 sector size (256,512,128)
*                                      bit 4,3 drive select (0,1,2,3)
*                                      bit 2,1,0 head select (0-7)
wd_secsize equ     %00000000           256 byte sectors
wd_sz_512  equ     %00100000           512 byte sectors
wd_sel0    equ     %00000000           select drive zero
wd_sel1    equ     %00001000           select drive one
wd_sel2    equ     %00010000           select drive two
wd_sel3    equ     %00011000           select drive three

wd_status  equ     wd1000+7            status (read only)
*                                      bit 7 busy
*                                      bit 6 ready
*                                      bit 5 write fault
*                                      bit 4 seek complete
*                                      bit 3 data request
*                                      bit 2,1 unused
*                                      bit 0 error (code in wd_error
wd_cmd     equ     wd1000+7            command (write only)
wd_restore equ     %00010110           restore with 3ms step rate
wd_seek    equ     %01110000           seek with 10us step rate
wd_read    equ     %00101000           read sector DMA
wd_write   equ     %00110000           write sector
wd_format  equ     %01010000           format track (SPECIAL USAGE)
*
W5STAT equ dmacc1 channel control register
W5CMD equ wd_cmd WD1000 command register

*
*  Special device addresses
*

BASACI equ $E000
SRLPRT0 equ $E070
SRLPRT1 equ $E074
PIA0 equ $E062 gimix parallel port (pia)

contab equ *

strm fcb 12 number of terminals
stsk fcb 48 number of tasks
siob fcb 64 number of io buffers
schl fcb 64 number of character lists
sfdn fcb 64 number of fdn entries
stxt fcb 20 number of text entries
smnt fcb 5 number of mounts
stim fcb 24 number of timeouts allowed
slok fcb 32 number of lock table entries
srtd fdb 4 root device number
sppd fdb 4 pipe device number
sswd fdb 4 swap device number
stlm fcb 0 time limit in 25.6 X seconds (0 disables)
sfil fdb 500 max file size for reg user
scon fdb BASACI console terminal address (acia)
sconbr fcb 0 Baud Rate value for system console
smxj fcb MAXJOB max user task count
stmz fdb 300 time zone (minutes west of gmt)
sdlt fcb 1 daylight savings here (0 if not)
sphz fcb 0 non-zero if power line is 50HZ
stup fcb 0 auto update time (0 disables) - value*4
smxm fcb NBLKS maximum mem segments per task
SWTPCvii fcb 0 non SWTPC vii system
DATsense fcb $FF SWTPC half inverted DAT form
ROMmap fdb $F1F0 Map registers for $E000-$FFFF
NMIhan fdb 0 ** Use ROM NMI handler **
SWI2han fdb 0 ** Also for SWI2 **

*
* Interrupt Handler Table
*    Used to decide which device generated an interrupt
* and how to process it.
*

inttab
 fcb N_intdev number of interrupt devices
* tty 0
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb BASACI+$00 status register
 fdb 0,0 No Baud Rate Generators
 fdb tintr tty interrupt routine
 fdb 0 device number
* tty 1
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb BASACI+$04 status register
 fdb 0,0 No Baud Rate Generators
 fdb tintr tty interrupt routine
 fdb 1 device number
 if 0
* tty 2
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb BASACI+$10 status register
 fdb 0,0 No Baud Rate Generators
 fdb tintr tty interrupt routine
 fdb 2 device number
* tty 3
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb BASACI+$14 status register
 fdb 0,0 No Baud Rate Generators
 fdb tintr tty interrupt routine
 fdb 3 device number
* tty 4
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb BASACI+$20 status register
 fdb 0,0 No Baud Rate Generators
 fdb tintr tty interrupt routine
 fdb 4 device number
* tty 5
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb BASACI+$24 status register
 fdb 0,0 No Baud Rate Generators
 fdb tintr tty interrupt routine
 fdb 5 device number
* tty 6
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb BASACI+$30 status register
 fdb 0,0 No Baud Rate Generators
 fdb tintr tty interrupt routine
 fdb 6 device number
* tty 7
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb BASACI+$34 status register
 fdb 0,0 No Baud Rate Generators
 fdb tintr tty interrupt routine
 fdb 7 device number
* tty 8
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb BASACI+$40 status register
 fdb 0,0 No Baud Rate Generators
 fdb tintr tty interrupt routine
 fdb 8 device number
* tty 9
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb BASACI+$44 status register
 fdb 0,0 No Baud Rate Generators
 fdb tintr tty interrupt routine
 fdb 9 device number
* tty 10
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb BASACI+$50 status register
 fdb 0,0 No Baud Rate Generators
 fdb tintr tty interrupt routine
 fdb 10 device number
* tty 11
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb BASACI+$54 status register
 fdb 0,0 No Baud Rate Generators
 fdb tintr tty interrupt routine
 fdb 11 device number
* serial printer
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb SRLPRT0 status register
 fdb 0,0 No Baud Rate Generators
 fdb spntr interrupt routine
 fdb $0500 device number
* serial printer two
 fcb 0,0 ACIA
 fcb %10000000 int mask
 fdb SRLPRT1 status register
 fdb 0,0 No Baud Rate Generators
 fdb spntr interrupt routine
 fdb $0501 device number
* parallel printer
 fcb 1,0 PIA
 fcb %10000000 int mask
 fdb PIA0+1 status register
 fdb 0,0 No Baud Rate Generators
 fdb ppint interrupt routine
 fdb $0600 device number
 endif
*
N_intdev equ (*-inttab-1)/INTSIZ
*
intend equ *


*
* fnttab
*
* Interrupt table for firq type interrupts.  It is
* the same as inttab above.
*

fnttab
fntend equ *


 pag

*
* Device tables
*

* Character table

chrtab
* tty device
 fdb ttopn tty open routine
 fdb ttcls tty close routine
 fdb ttrd tty read routine
 fdb ttwr tty write routine
 fdb ttspc special routine
* mem device
 fdb nuldev mem open
 fdb nuldev mem close
 fdb mdrd mem read
 fdb mdwr mem write
 fdb nuldev mem special
* null device
 fdb nuldev null dev open
 fdb nuldev null dev close
 fdb nuldrd null device read
 fdb nuldwr null device write
 fdb nuldev null special
* floppy disk (character)
 fdb fchop fd open
 fdb fchcl fd close
 fdb fchrd fd read
 fdb fchwr fd write
 fdb fchsp fd special
* cmi character drivers
 fdb cdcop cds open
 fdb cdccl cds close
 fdb cdcrd cds read
 fdb cdcwr cds write
 fdb cdcsp special
* serial printer drivers
 fdb spopn serial open
 fdb spcls serial close
 fdb nodev serial read
 fdb spwrt serial write
 fdb nuldev special
* parallel printer driver
 fdb ppopn parallel open
 fdb ppcls parallel close
 fdb nodev parallel read
 fdb ppwrt parallel write
 fdb nuldev special
* dummy entry for NEC
 rzb 5*2
* SWTPC 5" Winchester
 fdb w5cop cds open
 fdb w5ccl cds close
 fdb w5crd cds read
 fdb w5cwr cds write
 fdb w5csp special
** * floppy disk (character) DMF3
**  fdb fch3op fd open
**  fdb fch3cl fd close
**  fdb fch3rd fd read
**  fdb fch3wr fd write
**  fdb fch3sp fd special
 rzb 5*2
* Archive Tape
 fdb atopen open Archive Tape
 fdb atclose close Archive Tape
 fdb atread read Archive Tape
 fdb atwrite write Archive Tape
 fdb atspcl special
*
CHRDEV equ (*-chrtab)/DEVSIZ

* Block device table

blktab
 fdb BDopen,BD0open open routine
 fdb BDclose,BD0close close routine
 fdb BDio,BD0io main io routine
 fdb dmfdt device table pointer
 fcb BD0max
BLKDEV equ (*-blktab)/BLKSIZ

* Block Device 0 Open table
BD0open
DMF2minor equ (*-BD0open)/2 Minor Device for DMF2 Floppies
DMF2major equ 0
 fdb dmfopn fd0
 fdb dmfopn fd1
 fdb dmfopn fd2
 fdb dmfopn fd3
CMIminor equ (*-BD0open)/2
CMImajor equ 0
 fdb cmiopen hd0
 fdb cmiopen hd1
W5minor equ (*-BD0open)/2
W5major equ 0
 fdb w5open w0
 fdb w5open w1
 fdb w5open w2
 fdb w5open w3
ATminor equ (*-BD0open)/2
ATmajor equ 0
AT_DVN equ (ATmajor<<8)+ATminor
 fdb ATopen at0
BD0max equ (*-BD0open)/2

* Block Device 0 Close Table
BD0close
 fdb dmfcls fd0
 fdb dmfcls fd1
 fdb dmfcls fd2
 fdb dmfcls fd3
 fdb cmiclose hd0
 fdb cmiclose hd1
 fdb w5close w0
 fdb w5close w1
 fdb w5close w2
 fdb w5close w3
 fdb ATclose

* Block Device 0 I/O Table
BD0io
 fdb dmfio fd0
 fdb dmfio fd1
 fdb dmfio fd2
 fdb dmfio fd3
 fdb cmisto hd0
 fdb cmisto hd1
 fdb w5sto w0
 fdb w5sto w1
 fdb w5sto w2
 fdb w5sto w3
 fdb ATio

*
* Device Tables
*
dmfdt rzb DVTSIZ device table
cmidt equ dmfdt
w5dt equ dmfdt
at_dt equ dmfdt
*
* Floppy disk time-out stuff
*
FD5time equ 50 5.0 seconds
FD5cnt fcb 0

* buffer header for character device

fchbuf rzb HDRSIZ buffer header

*
* Tables for serial printers
*

SPBFSZ equ 100 buffer size

* tables and buffers

sptabl
 if 0
 fdb spbf0 buffer 0
 fdb SRLPRT0 acia 0
 fdb spbf1 buffer 1
 fdb SRLPRT1 acia 1
 endif
SPMAX equ (*-sptabl)/4-1

 if 0
spbf0 rzb SPBFSZ buffer 0
spbf1 rzb SPBFSZ buffer 1
 endif

* structure storage

spstrc rzb (SPMAX+1)*SPSZ

*
* Tables for Parallel Printers
*

PPstr
 fdb PIA0 PIA address
 fcb 0 Character count
 fcb 0 Busy flag
 fdb 0,0 Queue pointers
 rzb PPBUFSIZ actual buffer
*
PPMAX equ (*-PPstr)/PPSIZ-1
