  CMT':

  ப  :
 
b[1024] (cache buffer size) - ࠧ   , ᯮ㥬 
"". 1024 砥 ᫥騩 ࠧ  : (1024 * 8) .
 㦭   ⥯  (2, 4, 8,..., 512,... 4096...)

c[10] (cycles) - ⢮ 横 ஢ન 

r[5]  (read) - ⢮ 横 ⥭   (1 ࠧ 뢠
             -  ࠧ 뢠  ஢)

p[00AA55BB] (pattern) - ᪠, ன 㤥  
(8 ⭠  - 4 ,   16- ଥ)

a[7] (adder) - 䨪, ਡ  ᪥ १  横 ஢ન
               ( 10- ଥ),  㬮砭 a[0] ..  .

o (ordinary) - ᫨   ⮨ SSE ᮢ⨬ ,   㪠 CMT
               ᯮ짮  MOV 樨.

  ࠬ  易⥫,  㬮砭 ᯮ ⠪:
[50], r[1], p[55555555] , a[0]

᫨  ন SSE,  㬮砭 㤥 ᯮ짮 MOVNTQ
. 
ਬ: :\>cmt.com c[10] r[3] p[55555555] a[7]       ; Enter

 묨 ᪮    ஡,   १
 ।᪠㥬 (প ணࠬ஢  ᥬ).
 㤥 뢠 ઠ   ﬨ: 55555555:AAAAAAAA.
᫨ 䨪  㪠,  㬮砭 ᯮ 0 - ᪠  
    .

; * * * * * * * 
 ᨨ 0.9
 -  ⢨ ଠ樨  "Cache Line Size"  Pentium II(III, Celeron)
楤 뢠 ଠ樨     Intel  
 ⨬쭮. ணࠬ ࠢ쭮 ࠡ⠥   
Intel - 砫쭮 ᠫ  Athlon'.

, ணࠬ ᯮ  movntq,    Intel, 稭  Pentium III(Celeron 2) ( ७ SSE),    AMD, 稭  Athlon.   ⥫쭮 ᪮  ଠ樨  .

   ন  , ᯮ  
樨 뫪 : mov   memory, eax  ..

; * * * * * *
 ᨨ 0.91
 ⮩ ।樨  ⥭() "Cache Line Size"  Intel 
(Pentium (I, MMX, II, III, Celeron)), ⮬   - ᪮ 뢠 
ଠ樨     Intel (஬ Pentium 4)   
⨬쭮,  ᪮  ࠢ쭮.

; * * * * * *
 ᨨ 0.92
 ࠢ   ணࠬ  ( ᪮).




CrazyMemTester ᠫ 㤥 3  (㦥 4- -  2002)
  ⥬ () 
᪮ 樮쭮 孨᪮ 㭨
⨬ ᠭ (.. ).

ᠫ ࠤ 㤮⢮७ ᮡ⢥ ⢠ ⭮⥫쭮
 ⨬樨 ணࠬ  ஢ x86 ⥪,
ন   権.
 ⠪ ⭮⥫쭮  ன ਭ㤨⥫쭮 㧪
⮪ ଠ樨    .
 ⨣  뢠   ( 4-, 8- ),
 뢠  64-      ( Athlon`).
   ⮬,   뢠 ଠ樨  
(ਬ 㧪 4-   ॣ: mov eax, memory_var)
    ⮫쪮  4 ,  ᫥騥 60 ᫥ , .. 64 
   뢠.
       128   !
쭥襥 饭  㦥 ⠭  ਢ  ⮬,   
 砥  㦥  ,    ,      "⮯"
  饥 ६ ( 2002) ⥣஢    ࠡ⠥  
⮩    ன ࠡ⠥   (2,4 , ᫨  訡? :).


  Intel Pentium - Pentium III  稭, - ( ᫮
 ᮪᭨,    Celeron`) ࠢ 32- ⠬.
   祭  襣     ணࠬ 
⨯ CPUInfo  ࠧ ଠ樨  . 
 ࠧ ଠ樨  . 
筮  룫廊 ⠪: xx byte line size, xx Byte/Line, Line Size  ..


 ⠫쭮  ਥ ⨬樨    (  ⮫쪮)
   㬥:
AMD Athlon(tm) Processor x86 Code Optimization Guide,
    ᠩ AMD (www.amd.ru).
㬥 㡫  ଠ pdf  䠩 뢠 22007.pdf

ਢ ᪮쪮 ப  ⮣ 㬥 ⭮⥫쭮 ன 㧪
  .
// * * * * * * * * * * * * * * * * * * * * * *

22007J-August 2001               AMD Athlon(tm) Processor x86 Code Optimization

Memory Copy: Step 9
(final)

In the final optimization to the memory copy code, the
technique called block prefetch is applied. Much as read
grouping gave a boost to performance, block prefetch is an
extreme extension of this idea. The strategy is to read a large
stream of sequential data from main memory into the cache,
without any interruptions.
In block prefetch, the MOV instruction is used, rather than the
software prefetch instruction. Unlike a prefetch instruction,
the MOV instruction cannot be ignored by the CPU. The result
is that a series of MOVs will force the memory system to read
sequential, back-to-back address blocks, which maximizes
memory bandwidth.
And because the processor always loads an entire cache line
(e.g. 64 bytes) whenever it accesses main memory, the block
prefetch MOV instructions only need to read ONE address per
cache line. Reading just one address per cache line is a subtle
trick, which is essential in achieving maximum read
performance.
// * * * * * * * * * * * * * * * * * * * * * *

ணࠬ ஢    ࠬ:
AMD 5x86-133-PR75, AMD K6-2-300, Cyrix PR166, Celeron-450
Athlon 800, 1000, Morgan 1000 (  ࠡ⠫ :)

 ᮦ,    뫮   ணࠬ  Pentium 4 ⠪     ࠭ । 孨᪨ ୮ ࠬ 㤥⮢  :).

  १ ⮢:
訡    :(

 뢠   
Athlon 800(100 Bus), ASUS Via133, 	 = 700 Mb/s
Athlon 1000(133 Bus), Soltek Via133A     = 780 Mb/s
Morgan 1000(100 Bus), NoName Via133A     = 750 Mb/s 

   :
Athlon 800(100 Bus), ASUS Via133, 	 = 814 Mb/s
Athlon 1000(133 Bus), Soltek Via133A     = 990 Mb/s
Morgan 1000(100 Bus), NoName Via133A     = 1000 Mb/s 

 ⥮ਨ, ᨬ쭠 ய᪭ ᯮᮡ 64-ࠧ來 ,
ࠡ饩   133  ⠢ = 133 * 8 = 1064 /

᫨   ᯫ樨    祭 ᪮ 
⥮᪨ ,    - 譮 ७ ६
  ⥭,  祭    믮
讥 ⢮ ( 10) 横 ஢ન.
 㢥祭 ⢠ 横, 譮 㬥蠥  祭 ᪮⥩
  ⥮᪨ ⨬ ।.

ணࠬ ᨬ쭮 ⨬஢  ஢ Athlon
 , ᪮쪮  ,  ஫  ⥪ x86.
  ଠ    ⠪ (. ) ᪮ﬨ 
猪  ᨫ쭮 ॢ.  - 蠫  㪨 
 ⮫   ᭮ ஢ ࠢ쥢?...
- ਬ୮ ⠪      ୮ ,  ࠡ⠥ 
 ணࠬ.

⠪,   :
㤥 ணࠬ,  ⥭   ५  :);
॥ ᥣ, ୮ ᤥ  ;
, ,   -⠪  ᯮ짮  ⢥ 笠-ணࠬ,
饩 ᪮ ⮪  ଠ樥  ஬    設⢠ ᮢ६ ஢  
࠭  .


ணࠬ ।⠢ 筮  ᯫ⭮ 
(, ⠬ - GNU Public License   ⠪ :),
 室 .

,   / ணࠬ  ணࠬ⮢, ࠡ  ணࠬ,
騬 ,   ࠢ ந⥫쭮
CPU/Chipset/Memory, 㤥⮢,    ਭ樯 쭮 ⨬樨
ࠡ  ( ⭮ -  )  㣨 䠭⮢ :).

:
tasm cmt.asm /m
tlink cmt.obj /t /3

    - :
boundmen@mail.od.ua  
㤥 ६ - ⢥.

 㢠, Alex.